1. Field of the Invention
The present invention relates to a semiconductor fabrication process. More particularly, the present invention relates to a method of fabricating a passivation layer.
2. Description of the Related Art
In the manufacturing of semiconductors, a large number of steps is carried out to form logic and memory devices as well as interconnects electrically connected with those devices on a silicon wafer. After forming the interconnects, a patterned metallic layer is frequently formed over the wafer to serve as electrical contacts for connecting the devices and interconnects with corresponding external devices. To protect various devices on the wafer, an additional passivation layer is often formed over the substrate. In general, the passivation layer includes a silicon oxide layer and a silicon nitride layer. The silicon oxide layer mainly serves as an insulator and a stress reliever and the silicon nitride layer mainly serves as a barrier preventing the penetration of moisture.
Conventionally, the passivation layer is formed by forming silicon oxide over the patterned metallic layer and then forming silicon nitride over the silicon oxide layer. To prevent the heat generated in a chemical vapor deposition process from affecting the interconnects and devices underneath the metallic layer, a cooler deposition process such as the plasma-enhanced chemical vapor deposition process is performed. The plasma-enhanced chemical vapor deposition process can be directly applied to form a complete silicon oxide layer. Alternatively, the plasma-enhanced chemical deposition process is applied to form a high-density silicon oxide film over the patterned metallic layer first and then a semi-atmospheric chemical vapor deposition process is performed to form a thick silicon oxide layer over the silicon oxide film. And then, a following plasma plasma-enhanced chemical vapor deposition is performed again.
However, using a plasma-enhanced chemical vapor deposition process to form a silicon oxide layer often leads to a few problems. In the deposition process, when the reactive gases are constantly bombarded by plasma to make the gases ionized, the surface of the wafer is also bombarded by plasma. Therefore, the metallic layer over the surface of the wafer or the device underneath the metallic layer may lead to some structural or electrical damage. These damages to the logic or memory devices may lead to short circuit or device leakage problems. In particular, structural damage to a memory device often leads to a drop in charge storage capacity and hence a shortening of data retention time.